The present invention relates generally to digital transmission systems, and more particularly to clock regeneration using a phase-locked loop.
In 16-level quadrature amplitude modulation, a technique currently in use for high efficient spectral utilization, an incoming digital bit stream is converted by a serial-to-parallel converter to four parallel bit streams and time-compressed to allow insertion of redundant bits and quadrature amplitude modulation is effected upon a carrier with the bit streams. To effect these conversion and modulation, the clock information of the incoming bit stream is detected using a tank circuit tuned to the clock frequency. However, a dropout in the incoming bit stream causes the timing of the serial-to-parallel conversion to be seriously affected. More specifically, the serial-to-parallel converter includes a counter that divides the clock signal by a factor of four. The lower-frequency clock signal which is used to effect the serial-to-parallel conversion is fed to a time-compression and scrambling circuit where it is converted to a higher frequency at which the parallel bit streams are time-compressed to allow for insertion of redundant bits. This higher-frequency clock is generated by a circuit including a phase-locked loop. This phase-locked loop has a transient response time which is determined in consideration of the response time for clock regeneration at the receiving end of the digital transmission link. A dropout in the incoming bit stream would cause the frequency dividing counter to stop. Upon recovery, it resumes count operation starting with the count where it is stopped. Because of the indefiniteness of the count where the count operation is restarted, there is a discrete amount of phase shift at the output of the counter which amounts to an integral multiple of 90 degrees. The phase-locked loop by which the higher-frequency clock is generated cannot follow the discrete phase shift because of its large response time. Therefore, the higher-frequency clock is out of phase with the correct timing, resulting in a loss of data bits or a regeneration of same data bits. The transient response time of the higher-frequency phase-locked loop is at a maximum when the phase shift is 180 degrees, typically in a range between several milliseconds to several tens of milliseconds. Thus, even if the dropout lasts for as little as a few hundreds nanoseconds, bit errors can occur, which is likely to be interpreted as a circuit failure.